URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [stable_0_2_0_rc2/] [or1ksim/] [cache/] - Rev 1780

Rev	Log message	Author	Age	Path
1099	cvs bug fixed	markom	7872d 16h	/or1k/tags/stable_0_2_0_rc2/or1ksim/cache/
1085	Bug fixed.	simons	7885d 07h	/or1k/tags/stable_0_2_0_rc2/or1ksim/cache/
997	PRINTF should be used instead of printf; command redirection repaired	markom	7974d 19h	/or1k/tags/stable_0_2_0_rc2/or1ksim/cache/
992	A bug when cache enabled and bus error comes fixed.	simons	7976d 11h	/or1k/tags/stable_0_2_0_rc2/or1ksim/cache/
970	Testbench is now running on ORP architecture platform.	simons	7982d 06h	/or1k/tags/stable_0_2_0_rc2/or1ksim/cache/
884	code cleaning - a lot of global variables moved to runtime struct	markom	8018d 18h	/or1k/tags/stable_0_2_0_rc2/or1ksim/cache/
876	Beta release of ATA simulation	rherveille	8026d 05h	/or1k/tags/stable_0_2_0_rc2/or1ksim/cache/
638	TLBTR CI bit is now working properly.	simons	8177d 07h	/or1k/tags/stable_0_2_0_rc2/or1ksim/cache/
631	Real cache access is simulated now.	simons	8180d 06h	/or1k/tags/stable_0_2_0_rc2/or1ksim/cache/
626	store buffer added	markom	8180d 19h	/or1k/tags/stable_0_2_0_rc2/or1ksim/cache/