URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [stable_0_2_0_rc2/] [or1ksim/] [cpu/] - Rev 206

Rev	Log message	Author	Age	Path
129	Added code to inject insn from Debug Unit DIR	chris	8419d 11h	/or1k/tags/stable_0_2_0_rc2/or1ksim/cpu/
128	Added code to check debug unit after an exception	chris	8419d 11h	/or1k/tags/stable_0_2_0_rc2/or1ksim/cpu/
123	Bugs fixed: - l.rfe temporarly disables exceptions - l.sys does PC -= 4 - breakpoints now supported at peripheria locations - uart0.rt/.tx nonexistent file segment fault Other modifications: - replaced string names to instruction indexes - execute.c executes specified (in ISA table) function - modified ISA table - flag needed for gdb - added or32.c, which supports or32.h - added new instructions l.mac, l.msb, l.maci, l.macrc and their executing functions (opcodes to be revisited) - added header acconfig.h - modified configuration files	markom	8425d 09h	/or1k/tags/stable_0_2_0_rc2/or1ksim/cpu/
102	Major update to include PM, PIC, Cache Mngmnt and non-interactive mode.	lampret	8450d 18h	/or1k/tags/stable_0_2_0_rc2/or1ksim/cpu/
99	* empty log message *	lampret	8465d 18h	/or1k/tags/stable_0_2_0_rc2/or1ksim/cpu/
98	Return value register is now r9.	lampret	8465d 18h	/or1k/tags/stable_0_2_0_rc2/or1ksim/cpu/
90	Added tick timer.	lampret	8496d 02h	/or1k/tags/stable_0_2_0_rc2/or1ksim/cpu/
83	Updates.	lampret	8497d 09h	/or1k/tags/stable_0_2_0_rc2/or1ksim/cpu/
82	Changed pctemp to pcnext.	lampret	8497d 09h	/or1k/tags/stable_0_2_0_rc2/or1ksim/cpu/
77	Regular update.	lampret	8650d 15h	/or1k/tags/stable_0_2_0_rc2/or1ksim/cpu/