URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [stable_0_2_0_rc2/] [or1ksim/] [cpu/] - Rev 458

Rev	Log message	Author	Age	Path
378	cleanup in testbench; pc divided into ppc and npc	markom	8257d 00h	/or1k/tags/stable_0_2_0_rc2/or1ksim/cpu/
377	cleanup in testbench; pc divided into ppc and npc	markom	8257d 00h	/or1k/tags/stable_0_2_0_rc2/or1ksim/cpu/
374	* empty log message *	simons	8257d 16h	/or1k/tags/stable_0_2_0_rc2/or1ksim/cpu/
371	steps toward joining or32.c and opcode/or32.h of or1ksim and gdb; decode.c moved to or32.c	markom	8257d 23h	/or1k/tags/stable_0_2_0_rc2/or1ksim/cpu/
361	set config command added; config struct has been divided into two structs - config and runtime; -f option allows multiple config scripts	markom	8263d 01h	/or1k/tags/stable_0_2_0_rc2/or1ksim/cpu/
355	uart VAPI model improved; changes to MC and eth.	markom	8263d 21h	/or1k/tags/stable_0_2_0_rc2/or1ksim/cpu/
349	Some bugs regarding cache simulation fixed.	simons	8267d 13h	/or1k/tags/stable_0_2_0_rc2/or1ksim/cpu/
344	added acv test for uart; sim debug now has verbose levels; lot of bugs fixed in uart model	markom	8269d 21h	/or1k/tags/stable_0_2_0_rc2/or1ksim/cpu/
327	simulate_dc_mmu_load() was calling insn cache/mmu routines instead of data cache/mmu. Fixed.	lampret	8272d 07h	/or1k/tags/stable_0_2_0_rc2/or1ksim/cpu/
309	more tests run; added cfg capabilities for tests	markom	8275d 18h	/or1k/tags/stable_0_2_0_rc2/or1ksim/cpu/