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Subversion Repositories or1k

[/] [or1k/] [tags/] [stable_0_2_0_rc2/] [or1ksim/] [cpu/] [or1k/] - Rev 1529

Rev	Log message	Author	Age	Path
1382	Nir Mor: Implemented DCCFGR, ICCFGR, DMMUCFGR and IMMUCFGR spr registers.	nogj	7079d 04h	/or1k/tags/stable_0_2_0_rc2/or1ksim/cpu/or1k/
1376	aclocal && autoconf && automake	phoenix	7098d 04h	/or1k/tags/stable_0_2_0_rc2/or1ksim/cpu/or1k/
1354	typing fixes	phoenix	7113d 01h	/or1k/tags/stable_0_2_0_rc2/or1ksim/cpu/or1k/
1350	Mark a simulated cpu address as such, by introducing the new oraddr_t type	nogj	7113d 23h	/or1k/tags/stable_0_2_0_rc2/or1ksim/cpu/or1k/
1344	* Avoid doing a store in every instruction executed by storeing the instruction function unit in or32_opcodes	nogj	7127d 02h	/or1k/tags/stable_0_2_0_rc2/or1ksim/cpu/or1k/
1342	* Fix generate.c to produce a execgen.c with less warnings. * Fix the --enable-simple configure option.	nogj	7127d 03h	/or1k/tags/stable_0_2_0_rc2/or1ksim/cpu/or1k/
1341	Mark wich operand is the destination operand in the architechture definition	nogj	7127d 03h	/or1k/tags/stable_0_2_0_rc2/or1ksim/cpu/or1k/
1338	l.ff1 instruction added	andreje	7143d 01h	/or1k/tags/stable_0_2_0_rc2/or1ksim/cpu/or1k/
1319	cpu/sim memory accesses separation, tick, exception, nr. of operands, cycles count,... corrections.	phoenix	7230d 17h	/or1k/tags/stable_0_2_0_rc2/or1ksim/cpu/or1k/
1316	added a warning	phoenix	7248d 15h	/or1k/tags/stable_0_2_0_rc2/or1ksim/cpu/or1k/