URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [stable_0_2_0_rc2/] [or1ksim/] [peripheral/] - Rev 647

Rev	Log message	Author	Age	Path
445	Reading GPIO input reg now also returns values on output bits	erez	8240d 14h	/or1k/tags/stable_0_2_0_rc2/or1ksim/peripheral/
444	Added GPIO simulation	erez	8240d 23h	/or1k/tags/stable_0_2_0_rc2/or1ksim/peripheral/
439	Added "fake" JTAG proxy log to vapi log file	erez	8241d 07h	/or1k/tags/stable_0_2_0_rc2/or1ksim/peripheral/
424	memory configuration file joined into .cfg file; *mem.cfg are obsolete; read-only and write-only memory is supported; memory logging is not yet supported; update of testbench - only cache test fails, since it writes to RO memory	markom	8242d 10h	/or1k/tags/stable_0_2_0_rc2/or1ksim/peripheral/
423	changed break behaviour and interrupt pending; interrupt line chabnged to 15; sync bug in mode switch	markom	8243d 06h	/or1k/tags/stable_0_2_0_rc2/or1ksim/peripheral/
418	Renamed ethernet's RX_BD_NUM to TX_BD_NUM (following change in original files)	erez	8244d 00h	/or1k/tags/stable_0_2_0_rc2/or1ksim/peripheral/
411	acv uart testsuite now works (without modem test)	markom	8246d 11h	/or1k/tags/stable_0_2_0_rc2/or1ksim/peripheral/
409	some minor changes to or1ksim; Testbench except.s modified. Interrupt test almost finished for uart ACV.	markom	8247d 11h	/or1k/tags/stable_0_2_0_rc2/or1ksim/peripheral/
408	Fixed errant rx_bd_num	erez	8248d 07h	/or1k/tags/stable_0_2_0_rc2/or1ksim/peripheral/
406	Renamed ethernet's RX_BD_ADR to RX_BD_NUM	erez	8248d 10h	/or1k/tags/stable_0_2_0_rc2/or1ksim/peripheral/