URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [stable_0_2_0_rc3/] - Rev 372

Rev	Log message	Author	Age	Path
352	OR1200_REGISTERED_OUTPUTS can now be enabled.	lampret	8302d 15h	/or1k/tags/stable_0_2_0_rc3/
351	Fixed some l.trap typos.	lampret	8302d 16h	/or1k/tags/stable_0_2_0_rc3/
350	For GDB changed single stepping and disabled trap exception.	lampret	8302d 18h	/or1k/tags/stable_0_2_0_rc3/
349	Some bugs regarding cache simulation fixed.	simons	8304d 06h	/or1k/tags/stable_0_2_0_rc3/
348	Added instructions on how to build configure.	ivang	8305d 14h	/or1k/tags/stable_0_2_0_rc3/
347	Added CRC32 calculation to Ethernet	erez	8306d 11h	/or1k/tags/stable_0_2_0_rc3/
346	Improved Ethernet simulation	erez	8306d 13h	/or1k/tags/stable_0_2_0_rc3/
345	Added check for net/ethernet.h (needed by ethernet simulator)	erez	8306d 13h	/or1k/tags/stable_0_2_0_rc3/
344	added acv test for uart; sim debug now has verbose levels; lot of bugs fixed in uart model	markom	8306d 15h	/or1k/tags/stable_0_2_0_rc3/
343	Small touches to test programs	erez	8306d 17h	/or1k/tags/stable_0_2_0_rc3/