URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [stable_0_2_0_rc3/] [or1ksim/] - Rev 97

Rev	Log message	Author	Age	Path
68	Added hook for l.sys 204. Changed SPR of flag (no more CCR)	lampret	8733d 20h	/or1k/tags/stable_0_2_0_rc3/or1ksim/
67	Added simulator "application load".	lampret	8733d 20h	/or1k/tags/stable_0_2_0_rc3/or1ksim/
66	Added another set of eval_ functions that should be used directly by simulator. evalsim_ and setsim_ don't go through MMU transaltion mechanism.	lampret	8733d 20h	/or1k/tags/stable_0_2_0_rc3/or1ksim/
65	Added DMMU stats.	lampret	8733d 20h	/or1k/tags/stable_0_2_0_rc3/or1ksim/
64	SPR bit definition moved to spr_defs.h.	lampret	8733d 20h	/or1k/tags/stable_0_2_0_rc3/or1ksim/
63	Fixed a bug in getsprbits/setsprbits functions (now mask can have arbitry alignment of bits).	lampret	8733d 20h	/or1k/tags/stable_0_2_0_rc3/or1ksim/
62	OR1K DMMU model.	lampret	8733d 21h	/or1k/tags/stable_0_2_0_rc3/or1ksim/
60	Memory model changed.	lampret	8769d 00h	/or1k/tags/stable_0_2_0_rc3/or1ksim/
55	Added 'dv' command for dumping memory as verilog model.	lampret	8784d 21h	/or1k/tags/stable_0_2_0_rc3/or1ksim/
54	Regular maintenance.	lampret	8784d 21h	/or1k/tags/stable_0_2_0_rc3/or1ksim/