OpenCores
URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [stable_0_2_0_rc3/] [or1ksim/] [peripheral/] - Rev 1518

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
1467 * Remove useless checks.
* Don't halt the sim when not really necessary.
nogj 7030d 11h /or1k/tags/stable_0_2_0_rc3/or1ksim/peripheral/
1465 Fix printing of uninitialised value nogj 7030d 11h /or1k/tags/stable_0_2_0_rc3/or1ksim/peripheral/
1463 Make the ethernet peripheral use the new debug channels nogj 7030d 11h /or1k/tags/stable_0_2_0_rc3/or1ksim/peripheral/
1461 Add an optional `enabled' paramter to every peripheral nogj 7030d 11h /or1k/tags/stable_0_2_0_rc3/or1ksim/peripheral/
1446 Cosmetic fixes nogj 7030d 11h /or1k/tags/stable_0_2_0_rc3/or1ksim/peripheral/
1400 Useing set_mem32 and eval_mem32 is incorrect. Use set_direct32 and eval_direct32 instead nogj 7030d 11h /or1k/tags/stable_0_2_0_rc3/or1ksim/peripheral/
1396 Remove useless use of floats nogj 7030d 12h /or1k/tags/stable_0_2_0_rc3/or1ksim/peripheral/
1394 Fix VAPI in the uart nogj 7030d 12h /or1k/tags/stable_0_2_0_rc3/or1ksim/peripheral/
1392 Make uart use the new trace functions nogj 7030d 12h /or1k/tags/stable_0_2_0_rc3/or1ksim/peripheral/
1390 * Change scheduler to count down to 0 instead of reaching a certain cycle
count.
* Change the SCHED_ADD interface to take a time out as the parameter instead of the number of cycles.
nogj 7030d 12h /or1k/tags/stable_0_2_0_rc3/or1ksim/peripheral/

< Prev 1 2

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.