OpenCores
URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [start/] [insight/] - Rev 1765

Rev

Filtering Options

Clear current filter

Rev Log message Author Age Path
344 added acv test for uart; sim debug now has verbose levels; lot of bugs fixed in uart model markom 8260d 10h /or1k/tags/start/insight/
263 configure for cpu; modified command line options markom 8272d 09h /or1k/tags/start/insight/
262 small bug in build_automata fixed; configure for memory markom 8272d 09h /or1k/tags/start/insight/
221 major changes to testbench; debug unit is moved to /debug; memory organization can be customized; UART from simons; overall cleanup markom 8281d 11h /or1k/tags/start/insight/
207 Several major changes to allow gdb to work with an Or1k implementation
that does not need a writeable PC. This version will use the breakpoint
vector and install a new vector into the EPC register, and then single
step out of the breakpoint exception. The breakpoint exception vector
must include only 2 commands: l.rfe and l.nop. Anything else and this
gdb version will fail w/ or1ksim.
chris 8308d 13h /or1k/tags/start/insight/
174 Few changes that should be done previously:
- machine.h replaced by spr_defs.h
- if reset label does not exist, boot from 0x0100
markom 8350d 12h /or1k/tags/start/insight/
151 Typo in the previous commit. Sorry. chris 8400d 15h /or1k/tags/start/insight/
150 Fixed some single stepping issues chris 8400d 15h /or1k/tags/start/insight/
149 Fixed bug where disassemble command caused a segmentation fault chris 8401d 17h /or1k/tags/start/insight/
146 Mofications to work with or1ksim JTAG based simulation chris 8402d 09h /or1k/tags/start/insight/

< Prev 1 2

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.