URL https://opencores.org/ocsvn/or1k_old/or1k_old/trunk

Subversion Repositories or1k_old

[/] [or1k_old/] [tags/] [hello-uart_v1_0/] - Rev 1782

Rev	Log message	Author	Age	Path
1193	disabled SRAM_GENERIC and added comment + corrected 'wb_err' into 'wb_err_o'	dries	7578d 09h	/or1k_old/tags/hello-uart_v1_0/
1192	disabled 'bench_defines.v' during synthesis + added define to specify usage of flash instruction address	dries	7578d 10h	/or1k_old/tags/hello-uart_v1_0/
1191	disabled 'bench_defines.v' during synthesis + added define to specify usage of flash instruction address	dries	7578d 10h	/or1k_old/tags/hello-uart_v1_0/
1188	Added support for rams with byte write access.	simons	7594d 09h	/or1k_old/tags/hello-uart_v1_0/
1186	Added support for rams with byte write access.	simons	7595d 08h	/or1k_old/tags/hello-uart_v1_0/
1184	Scan signals mess fixed.	simons	7602d 01h	/or1k_old/tags/hello-uart_v1_0/
1183	OpenRISC port of gdb-5.3 straightforwardly derived from gdb-5.0	sfurman	7606d 16h	/or1k_old/tags/hello-uart_v1_0/
1181	Initial import of unmodified gdb-5.3 source on vendor branch	sfurman	7606d 19h	/or1k_old/tags/hello-uart_v1_0/
1179	BIST interface added for Artisan memory instances.	simons	7610d 04h	/or1k_old/tags/hello-uart_v1_0/
1178	avoid another immu exception that should not happen	phoenix	7639d 16h	/or1k_old/tags/hello-uart_v1_0/