URL https://opencores.org/ocsvn/or1k_old/or1k_old/trunk

Subversion Repositories or1k_old

[/] [or1k_old/] [tags/] [rel-0-3-0-rc3/] [or1ksim/] [testbench/] - Rev 538

Rev	Log message	Author	Age	Path
484	Changed to support execution from various addresses.	simons	8264d 10h	/or1k_old/tags/rel-0-3-0-rc3/or1ksim/testbench/
483	Implemented some GPIO tests	erez	8264d 11h	/or1k_old/tags/rel-0-3-0-rc3/or1ksim/testbench/
480	RTL_SIM define added for shorter simulation runtime.	simons	8264d 14h	/or1k_old/tags/rel-0-3-0-rc3/or1ksim/testbench/
479	connection with gdb repaired; temp_except_delay removed; lot of except and debug code cleaned; sys 203 causes stall under gdb; non-sim memory area log bug fixed	markom	8264d 15h	/or1k_old/tags/rel-0-3-0-rc3/or1ksim/testbench/
478	Started adding acv_gpio testbench	erez	8264d 15h	/or1k_old/tags/rel-0-3-0-rc3/or1ksim/testbench/
476	Fixed warnings.	ivang	8264d 16h	/or1k_old/tags/rel-0-3-0-rc3/or1ksim/testbench/
475	l.jalr r9 is not used any more.	simons	8264d 17h	/or1k_old/tags/rel-0-3-0-rc3/or1ksim/testbench/
473	Added test flag templates.	ivang	8264d 20h	/or1k_old/tags/rel-0-3-0-rc3/or1ksim/testbench/
472	Removed MC initialization. Must be done in except_mc.S	ivang	8264d 20h	/or1k_old/tags/rel-0-3-0-rc3/or1ksim/testbench/
471	Removed MC initialization. Must be done in except_mc.S	ivang	8264d 20h	/or1k_old/tags/rel-0-3-0-rc3/or1ksim/testbench/