URL https://opencores.org/ocsvn/pci/pci/trunk

Subversion Repositories pci

[/] [pci/] [tags/] [asyst_2/] [rtl/] - Rev 108

Rev	Log message	Author	Age	Path
62	Added BIST signals for RAMs.	mihad	7967d 01h	/pci/tags/asyst_2/rtl/
60	Added support for Virtual Silicon two port RAM. Didn't run regression on it yet!	mihad	7975d 01h	/pci/tags/asyst_2/rtl/
59	Added meta flop module for easier meta stable FF identification during synthesis	mihad	7975d 03h	/pci/tags/asyst_2/rtl/
58	Removed all logic from asynchronous reset network	mihad	7980d 03h	/pci/tags/asyst_2/rtl/
57	Added completion expiration test for WB Slave unit. Changed expiration signalling	mihad	7980d 09h	/pci/tags/asyst_2/rtl/
56	Number of state bits define was removed	mihad	7981d 00h	/pci/tags/asyst_2/rtl/
55	Changed state machine encoding to true one-hot	mihad	7981d 00h	/pci/tags/asyst_2/rtl/
53	Updated for synthesis purposes. Gate level simulation was failing in some configurations	mihad	8014d 05h	/pci/tags/asyst_2/rtl/
51	Fixed a bug and provided testcase for it. Target was responding to configuration cycle type 1 transactions.	mihad	8014d 10h	/pci/tags/asyst_2/rtl/
50	Got rid of undef directives	mihad	8017d 02h	/pci/tags/asyst_2/rtl/