URL https://opencores.org/ocsvn/pci/pci/trunk

Subversion Repositories pci

[/] [pci/] [tags/] [asyst_2/] [rtl/] [verilog/] - Rev 104

Rev	Log message	Author	Age	Path
59	Added meta flop module for easier meta stable FF identification during synthesis	mihad	8007d 03h	/pci/tags/asyst_2/rtl/verilog/
58	Removed all logic from asynchronous reset network	mihad	8012d 03h	/pci/tags/asyst_2/rtl/verilog/
57	Added completion expiration test for WB Slave unit. Changed expiration signalling	mihad	8012d 09h	/pci/tags/asyst_2/rtl/verilog/
56	Number of state bits define was removed	mihad	8013d 00h	/pci/tags/asyst_2/rtl/verilog/
55	Changed state machine encoding to true one-hot	mihad	8013d 01h	/pci/tags/asyst_2/rtl/verilog/
53	Updated for synthesis purposes. Gate level simulation was failing in some configurations	mihad	8046d 06h	/pci/tags/asyst_2/rtl/verilog/
51	Fixed a bug and provided testcase for it. Target was responding to configuration cycle type 1 transactions.	mihad	8046d 10h	/pci/tags/asyst_2/rtl/verilog/
50	Got rid of undef directives	mihad	8049d 02h	/pci/tags/asyst_2/rtl/verilog/
49	Extracted distributed RAM module from wb/pci_tpram.v to its own file, got rid of undef directives	mihad	8049d 02h	/pci/tags/asyst_2/rtl/verilog/
48	Extracted distributed RAM module from wb/pci_tpram.v to its own file	mihad	8049d 02h	/pci/tags/asyst_2/rtl/verilog/