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[/] [pci/] [tags/] [asyst_2/] [rtl/] [verilog/] - Rev 110

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Rev Log message Author Age Path
63 Added additional testcase and changed rst name in BIST to trst mihad 7938d 18h /pci/tags/asyst_2/rtl/verilog/
62 Added BIST signals for RAMs. mihad 7941d 11h /pci/tags/asyst_2/rtl/verilog/
60 Added support for Virtual Silicon two port RAM. Didn't run regression on it yet! mihad 7949d 10h /pci/tags/asyst_2/rtl/verilog/
59 Added meta flop module for easier meta stable FF identification during synthesis mihad 7949d 12h /pci/tags/asyst_2/rtl/verilog/
58 Removed all logic from asynchronous reset network mihad 7954d 12h /pci/tags/asyst_2/rtl/verilog/
57 Added completion expiration test for WB Slave unit. Changed expiration signalling mihad 7954d 18h /pci/tags/asyst_2/rtl/verilog/
56 Number of state bits define was removed mihad 7955d 09h /pci/tags/asyst_2/rtl/verilog/
55 Changed state machine encoding to true one-hot mihad 7955d 09h /pci/tags/asyst_2/rtl/verilog/
53 Updated for synthesis purposes. Gate level simulation was failing in some configurations mihad 7988d 14h /pci/tags/asyst_2/rtl/verilog/
51 Fixed a bug and provided testcase for it. Target was responding to configuration cycle type 1 transactions. mihad 7988d 19h /pci/tags/asyst_2/rtl/verilog/

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