URL https://opencores.org/ocsvn/pci/pci/trunk

Subversion Repositories pci

[/] [pci/] [tags/] [asyst_2/] [rtl/] [verilog/] - Rev 111

Rev	Log message	Author	Age	Path
65	Cleaned up non-blocking assignments in combinatinal logic statements	mihad	7973d 12h	/pci/tags/asyst_2/rtl/verilog/
63	Added additional testcase and changed rst name in BIST to trst	mihad	7973d 16h	/pci/tags/asyst_2/rtl/verilog/
62	Added BIST signals for RAMs.	mihad	7976d 09h	/pci/tags/asyst_2/rtl/verilog/
60	Added support for Virtual Silicon two port RAM. Didn't run regression on it yet!	mihad	7984d 09h	/pci/tags/asyst_2/rtl/verilog/
59	Added meta flop module for easier meta stable FF identification during synthesis	mihad	7984d 10h	/pci/tags/asyst_2/rtl/verilog/
58	Removed all logic from asynchronous reset network	mihad	7989d 11h	/pci/tags/asyst_2/rtl/verilog/
57	Added completion expiration test for WB Slave unit. Changed expiration signalling	mihad	7989d 17h	/pci/tags/asyst_2/rtl/verilog/
56	Number of state bits define was removed	mihad	7990d 07h	/pci/tags/asyst_2/rtl/verilog/
55	Changed state machine encoding to true one-hot	mihad	7990d 08h	/pci/tags/asyst_2/rtl/verilog/
53	Updated for synthesis purposes. Gate level simulation was failing in some configurations	mihad	8023d 13h	/pci/tags/asyst_2/rtl/verilog/