URL https://opencores.org/ocsvn/pci/pci/trunk

Subversion Repositories pci

[/] [pci/] [tags/] [asyst_2/] [rtl/] [verilog/] - Rev 128

Rev	Log message	Author	Age	Path
77	Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed.	mihad	7888d 02h	/pci/tags/asyst_2/rtl/verilog/
73	Bug fixes, testcases added.	mihad	7894d 02h	/pci/tags/asyst_2/rtl/verilog/
72	* empty log message *	mihad	7941d 06h	/pci/tags/asyst_2/rtl/verilog/
71	Changed the code a bit to make it more readable. Functionality not changed in any way. More robust synchronization in fifos is still pending.	mihad	7948d 22h	/pci/tags/asyst_2/rtl/verilog/
69	Changed BIST signal names etc..	mihad	7986d 05h	/pci/tags/asyst_2/rtl/verilog/
68	Changed wrong signal name scanb_sen into scanb_en.	tadejm	7989d 15h	/pci/tags/asyst_2/rtl/verilog/
67	Changed BIST signals for RAMs.	tadejm	7989d 20h	/pci/tags/asyst_2/rtl/verilog/
66	Changed empty status generation in pciw_fifo_control.v	mihad	7993d 06h	/pci/tags/asyst_2/rtl/verilog/
65	Cleaned up non-blocking assignments in combinatinal logic statements	mihad	7996d 04h	/pci/tags/asyst_2/rtl/verilog/
63	Added additional testcase and changed rst name in BIST to trst	mihad	7996d 08h	/pci/tags/asyst_2/rtl/verilog/