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[/] [pci/] [tags/] [asyst_2/] [rtl/] [verilog/] - Rev 130

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Rev Log message Author Age Path
78 Old files with wrong names removed. mihad 7830d 05h /pci/tags/asyst_2/rtl/verilog/
77 Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed. mihad 7830d 05h /pci/tags/asyst_2/rtl/verilog/
73 Bug fixes, testcases added. mihad 7836d 06h /pci/tags/asyst_2/rtl/verilog/
72 *** empty log message *** mihad 7883d 10h /pci/tags/asyst_2/rtl/verilog/
71 Changed the code a bit to make it more readable.
Functionality not changed in any way.
More robust synchronization in fifos is still pending.
mihad 7891d 02h /pci/tags/asyst_2/rtl/verilog/
69 Changed BIST signal names etc.. mihad 7928d 09h /pci/tags/asyst_2/rtl/verilog/
68 Changed wrong signal name scanb_sen into scanb_en. tadejm 7931d 19h /pci/tags/asyst_2/rtl/verilog/
67 Changed BIST signals for RAMs. tadejm 7931d 23h /pci/tags/asyst_2/rtl/verilog/
66 Changed empty status generation in pciw_fifo_control.v mihad 7935d 10h /pci/tags/asyst_2/rtl/verilog/
65 Cleaned up non-blocking assignments in combinatinal logic statements mihad 7938d 08h /pci/tags/asyst_2/rtl/verilog/

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