URL https://opencores.org/ocsvn/pci/pci/trunk

Subversion Repositories pci

[/] [pci/] [tags/] [asyst_2/] [rtl/] [verilog/] - Rev 132

Rev	Log message	Author	Age	Path
81	Updated synchronization in top level fifo modules.	mihad	7818d 10h	/pci/tags/asyst_2/rtl/verilog/
79	Updated.	mihad	7821d 15h	/pci/tags/asyst_2/rtl/verilog/
78	Old files with wrong names removed.	mihad	7821d 16h	/pci/tags/asyst_2/rtl/verilog/
77	Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed.	mihad	7821d 16h	/pci/tags/asyst_2/rtl/verilog/
73	Bug fixes, testcases added.	mihad	7827d 16h	/pci/tags/asyst_2/rtl/verilog/
72	* empty log message *	mihad	7874d 20h	/pci/tags/asyst_2/rtl/verilog/
71	Changed the code a bit to make it more readable. Functionality not changed in any way. More robust synchronization in fifos is still pending.	mihad	7882d 12h	/pci/tags/asyst_2/rtl/verilog/
69	Changed BIST signal names etc..	mihad	7919d 19h	/pci/tags/asyst_2/rtl/verilog/
68	Changed wrong signal name scanb_sen into scanb_en.	tadejm	7923d 05h	/pci/tags/asyst_2/rtl/verilog/
67	Changed BIST signals for RAMs.	tadejm	7923d 10h	/pci/tags/asyst_2/rtl/verilog/