URL https://opencores.org/ocsvn/pci/pci/trunk

Subversion Repositories pci

[/] [pci/] [tags/] [asyst_2/] [rtl/] [verilog/] - Rev 81

Rev	Log message	Author	Age	Path
53	Updated for synthesis purposes. Gate level simulation was failing in some configurations	mihad	8023d 08h	/pci/tags/asyst_2/rtl/verilog/
51	Fixed a bug and provided testcase for it. Target was responding to configuration cycle type 1 transactions.	mihad	8023d 12h	/pci/tags/asyst_2/rtl/verilog/
50	Got rid of undef directives	mihad	8026d 04h	/pci/tags/asyst_2/rtl/verilog/
49	Extracted distributed RAM module from wb/pci_tpram.v to its own file, got rid of undef directives	mihad	8026d 04h	/pci/tags/asyst_2/rtl/verilog/
48	Extracted distributed RAM module from wb/pci_tpram.v to its own file	mihad	8026d 04h	/pci/tags/asyst_2/rtl/verilog/
47	Known issues repaired	mihad	8026d 10h	/pci/tags/asyst_2/rtl/verilog/
46	Include statement was enclosed in synosys translate off/on directive - repaired	mihad	8031d 04h	/pci/tags/asyst_2/rtl/verilog/
45	Added a few testcases. Repaired wrong reset value for PCI_AM5 register. Repaired Parity Error Detected bit setting. Changed PCI_AM0 to always enabled(regardles of PCI_AM0 define), if image 0 is used as configuration image	mihad	8032d 10h	/pci/tags/asyst_2/rtl/verilog/
35	Files updated with missing includes, resolved some race conditions in test bench	mihad	8177d 13h	/pci/tags/asyst_2/rtl/verilog/
33	Added some testcases, removed un-needed fifo signals	mihad	8193d 09h	/pci/tags/asyst_2/rtl/verilog/