URL https://opencores.org/ocsvn/pci/pci/trunk

Subversion Repositories pci

[/] [pci/] [tags/] [asyst_2/] [rtl/] [verilog/] - Rev 88

Rev	Log message	Author	Age	Path
57	Added completion expiration test for WB Slave unit. Changed expiration signalling	mihad	7954d 10h	/pci/tags/asyst_2/rtl/verilog/
56	Number of state bits define was removed	mihad	7955d 01h	/pci/tags/asyst_2/rtl/verilog/
55	Changed state machine encoding to true one-hot	mihad	7955d 02h	/pci/tags/asyst_2/rtl/verilog/
53	Updated for synthesis purposes. Gate level simulation was failing in some configurations	mihad	7988d 07h	/pci/tags/asyst_2/rtl/verilog/
51	Fixed a bug and provided testcase for it. Target was responding to configuration cycle type 1 transactions.	mihad	7988d 11h	/pci/tags/asyst_2/rtl/verilog/
50	Got rid of undef directives	mihad	7991d 03h	/pci/tags/asyst_2/rtl/verilog/
49	Extracted distributed RAM module from wb/pci_tpram.v to its own file, got rid of undef directives	mihad	7991d 03h	/pci/tags/asyst_2/rtl/verilog/
48	Extracted distributed RAM module from wb/pci_tpram.v to its own file	mihad	7991d 03h	/pci/tags/asyst_2/rtl/verilog/
47	Known issues repaired	mihad	7991d 09h	/pci/tags/asyst_2/rtl/verilog/
46	Include statement was enclosed in synosys translate off/on directive - repaired	mihad	7996d 03h	/pci/tags/asyst_2/rtl/verilog/