URL https://opencores.org/ocsvn/pci/pci/trunk

Subversion Repositories pci

[/] [pci/] [tags/] [rel_10/] - Rev 85

Rev	Log message	Author	Age	Path
60	Added support for Virtual Silicon two port RAM. Didn't run regression on it yet!	mihad	7976d 06h	/pci/tags/rel_10/
59	Added meta flop module for easier meta stable FF identification during synthesis	mihad	7976d 07h	/pci/tags/rel_10/
58	Removed all logic from asynchronous reset network	mihad	7981d 07h	/pci/tags/rel_10/
57	Added completion expiration test for WB Slave unit. Changed expiration signalling	mihad	7981d 13h	/pci/tags/rel_10/
56	Number of state bits define was removed	mihad	7982d 04h	/pci/tags/rel_10/
55	Changed state machine encoding to true one-hot	mihad	7982d 04h	/pci/tags/rel_10/
54	Changed Tsetup and Thold for WISHBONE models, due to difficulties encountered during gate level sim	mihad	8015d 06h	/pci/tags/rel_10/
53	Updated for synthesis purposes. Gate level simulation was failing in some configurations	mihad	8015d 09h	/pci/tags/rel_10/
52	Oops, never before noticed that OC header is missing	mihad	8015d 14h	/pci/tags/rel_10/
51	Fixed a bug and provided testcase for it. Target was responding to configuration cycle type 1 transactions.	mihad	8015d 14h	/pci/tags/rel_10/