URL https://opencores.org/ocsvn/pci/pci/trunk

Subversion Repositories pci

[/] [pci/] [tags/] [rel_10/] - Rev 88

Rev	Log message	Author	Age	Path
64	The testcase I just added in previous revision repaired	mihad	7931d 10h	/pci/tags/rel_10/
63	Added additional testcase and changed rst name in BIST to trst	mihad	7931d 12h	/pci/tags/rel_10/
62	Added BIST signals for RAMs.	mihad	7934d 05h	/pci/tags/rel_10/
60	Added support for Virtual Silicon two port RAM. Didn't run regression on it yet!	mihad	7942d 05h	/pci/tags/rel_10/
59	Added meta flop module for easier meta stable FF identification during synthesis	mihad	7942d 06h	/pci/tags/rel_10/
58	Removed all logic from asynchronous reset network	mihad	7947d 06h	/pci/tags/rel_10/
57	Added completion expiration test for WB Slave unit. Changed expiration signalling	mihad	7947d 12h	/pci/tags/rel_10/
56	Number of state bits define was removed	mihad	7948d 03h	/pci/tags/rel_10/
55	Changed state machine encoding to true one-hot	mihad	7948d 04h	/pci/tags/rel_10/
54	Changed Tsetup and Thold for WISHBONE models, due to difficulties encountered during gate level sim	mihad	7981d 05h	/pci/tags/rel_10/