URL https://opencores.org/ocsvn/pci/pci/trunk

Subversion Repositories pci

[/] [pci/] [tags/] [rel_10/] [rtl/] - Rev 115

Rev	Log message	Author	Age	Path
67	Changed BIST signals for RAMs.	tadejm	7922d 02h	/pci/tags/rel_10/rtl/
66	Changed empty status generation in pciw_fifo_control.v	mihad	7925d 13h	/pci/tags/rel_10/rtl/
65	Cleaned up non-blocking assignments in combinatinal logic statements	mihad	7928d 11h	/pci/tags/rel_10/rtl/
63	Added additional testcase and changed rst name in BIST to trst	mihad	7928d 15h	/pci/tags/rel_10/rtl/
62	Added BIST signals for RAMs.	mihad	7931d 08h	/pci/tags/rel_10/rtl/
60	Added support for Virtual Silicon two port RAM. Didn't run regression on it yet!	mihad	7939d 08h	/pci/tags/rel_10/rtl/
59	Added meta flop module for easier meta stable FF identification during synthesis	mihad	7939d 09h	/pci/tags/rel_10/rtl/
58	Removed all logic from asynchronous reset network	mihad	7944d 09h	/pci/tags/rel_10/rtl/
57	Added completion expiration test for WB Slave unit. Changed expiration signalling	mihad	7944d 15h	/pci/tags/rel_10/rtl/
56	Number of state bits define was removed	mihad	7945d 06h	/pci/tags/rel_10/rtl/