URL https://opencores.org/ocsvn/pci/pci/trunk

Subversion Repositories pci

[/] [pci/] [tags/] [rel_10/] [rtl/] [verilog/] - Rev 69

Rev	Log message	Author	Age	Path
45	Added a few testcases. Repaired wrong reset value for PCI_AM5 register. Repaired Parity Error Detected bit setting. Changed PCI_AM0 to always enabled(regardles of PCI_AM0 define), if image 0 is used as configuration image	mihad	8003d 09h	/pci/tags/rel_10/rtl/verilog/
35	Files updated with missing includes, resolved some race conditions in test bench	mihad	8148d 12h	/pci/tags/rel_10/rtl/verilog/
33	Added some testcases, removed un-needed fifo signals	mihad	8164d 08h	/pci/tags/rel_10/rtl/verilog/
32	Added include statement that was missing and causing errors	mihad	8172d 05h	/pci/tags/rel_10/rtl/verilog/
26	Modified testbench and fixed some bugs	mihad	8178d 03h	/pci/tags/rel_10/rtl/verilog/
23	* empty log message *	mihad	8196d 04h	/pci/tags/rel_10/rtl/verilog/
21	Repaired a few bugs, updated specification, added test bench files and design document	mihad	8196d 04h	/pci/tags/rel_10/rtl/verilog/
19	* empty log message *	mihad	8196d 05h	/pci/tags/rel_10/rtl/verilog/
18	* empty log message *	mihad	8196d 05h	/pci/tags/rel_10/rtl/verilog/
7	Updated all files with inclusion of timescale file for simulation purposes.	mihad	8315d 12h	/pci/tags/rel_10/rtl/verilog/