URL https://opencores.org/ocsvn/pci/pci/trunk

Subversion Repositories pci

[/] [pci/] [tags/] [rel_12/] - Rev 83

Rev	Log message	Author	Age	Path
58	Removed all logic from asynchronous reset network	mihad	7947d 13h	/pci/tags/rel_12/
57	Added completion expiration test for WB Slave unit. Changed expiration signalling	mihad	7947d 19h	/pci/tags/rel_12/
56	Number of state bits define was removed	mihad	7948d 10h	/pci/tags/rel_12/
55	Changed state machine encoding to true one-hot	mihad	7948d 11h	/pci/tags/rel_12/
54	Changed Tsetup and Thold for WISHBONE models, due to difficulties encountered during gate level sim	mihad	7981d 12h	/pci/tags/rel_12/
53	Updated for synthesis purposes. Gate level simulation was failing in some configurations	mihad	7981d 16h	/pci/tags/rel_12/
52	Oops, never before noticed that OC header is missing	mihad	7981d 20h	/pci/tags/rel_12/
51	Fixed a bug and provided testcase for it. Target was responding to configuration cycle type 1 transactions.	mihad	7981d 20h	/pci/tags/rel_12/
50	Got rid of undef directives	mihad	7984d 12h	/pci/tags/rel_12/
49	Extracted distributed RAM module from wb/pci_tpram.v to its own file, got rid of undef directives	mihad	7984d 12h	/pci/tags/rel_12/