URL https://opencores.org/ocsvn/pci/pci/trunk

Subversion Repositories pci

[/] [pci/] [tags/] [rel_12/] - Rev 86

Rev	Log message	Author	Age	Path
62	Added BIST signals for RAMs.	mihad	7944d 01h	/pci/tags/rel_12/
60	Added support for Virtual Silicon two port RAM. Didn't run regression on it yet!	mihad	7952d 00h	/pci/tags/rel_12/
59	Added meta flop module for easier meta stable FF identification during synthesis	mihad	7952d 02h	/pci/tags/rel_12/
58	Removed all logic from asynchronous reset network	mihad	7957d 02h	/pci/tags/rel_12/
57	Added completion expiration test for WB Slave unit. Changed expiration signalling	mihad	7957d 08h	/pci/tags/rel_12/
56	Number of state bits define was removed	mihad	7957d 23h	/pci/tags/rel_12/
55	Changed state machine encoding to true one-hot	mihad	7957d 23h	/pci/tags/rel_12/
54	Changed Tsetup and Thold for WISHBONE models, due to difficulties encountered during gate level sim	mihad	7991d 01h	/pci/tags/rel_12/
53	Updated for synthesis purposes. Gate level simulation was failing in some configurations	mihad	7991d 04h	/pci/tags/rel_12/
52	Oops, never before noticed that OC header is missing	mihad	7991d 08h	/pci/tags/rel_12/