URL https://opencores.org/ocsvn/pci/pci/trunk

Subversion Repositories pci

[/] [pci/] [tags/] [rel_5/] [rtl/] - Rev 81

Rev	Log message	Author	Age	Path
53	Updated for synthesis purposes. Gate level simulation was failing in some configurations	mihad	7977d 07h	/pci/tags/rel_5/rtl/
51	Fixed a bug and provided testcase for it. Target was responding to configuration cycle type 1 transactions.	mihad	7977d 11h	/pci/tags/rel_5/rtl/
50	Got rid of undef directives	mihad	7980d 03h	/pci/tags/rel_5/rtl/
49	Extracted distributed RAM module from wb/pci_tpram.v to its own file, got rid of undef directives	mihad	7980d 03h	/pci/tags/rel_5/rtl/
48	Extracted distributed RAM module from wb/pci_tpram.v to its own file	mihad	7980d 04h	/pci/tags/rel_5/rtl/
47	Known issues repaired	mihad	7980d 09h	/pci/tags/rel_5/rtl/
46	Include statement was enclosed in synosys translate off/on directive - repaired	mihad	7985d 04h	/pci/tags/rel_5/rtl/
45	Added a few testcases. Repaired wrong reset value for PCI_AM5 register. Repaired Parity Error Detected bit setting. Changed PCI_AM0 to always enabled(regardles of PCI_AM0 define), if image 0 is used as configuration image	mihad	7986d 09h	/pci/tags/rel_5/rtl/
35	Files updated with missing includes, resolved some race conditions in test bench	mihad	8131d 13h	/pci/tags/rel_5/rtl/
33	Added some testcases, removed un-needed fifo signals	mihad	8147d 08h	/pci/tags/rel_5/rtl/