URL https://opencores.org/ocsvn/pci/pci/trunk

Subversion Repositories pci

[/] [pci/] [tags/] [rel_6/] - Rev 77

Rev	Log message	Author	Age	Path
54	Changed Tsetup and Thold for WISHBONE models, due to difficulties encountered during gate level sim	mihad	8020d 15h	/pci/tags/rel_6/
53	Updated for synthesis purposes. Gate level simulation was failing in some configurations	mihad	8020d 18h	/pci/tags/rel_6/
52	Oops, never before noticed that OC header is missing	mihad	8020d 22h	/pci/tags/rel_6/
51	Fixed a bug and provided testcase for it. Target was responding to configuration cycle type 1 transactions.	mihad	8020d 23h	/pci/tags/rel_6/
50	Got rid of undef directives	mihad	8023d 15h	/pci/tags/rel_6/
49	Extracted distributed RAM module from wb/pci_tpram.v to its own file, got rid of undef directives	mihad	8023d 15h	/pci/tags/rel_6/
48	Extracted distributed RAM module from wb/pci_tpram.v to its own file	mihad	8023d 15h	/pci/tags/rel_6/
47	Known issues repaired	mihad	8023d 21h	/pci/tags/rel_6/
46	Include statement was enclosed in synosys translate off/on directive - repaired	mihad	8028d 15h	/pci/tags/rel_6/
45	Added a few testcases. Repaired wrong reset value for PCI_AM5 register. Repaired Parity Error Detected bit setting. Changed PCI_AM0 to always enabled(regardles of PCI_AM0 define), if image 0 is used as configuration image	mihad	8029d 21h	/pci/tags/rel_6/