URL https://opencores.org/ocsvn/pci/pci/trunk

Subversion Repositories pci

[/] [pci/] [tags/] [rel_6/] [rtl/] - Rev 154

Rev	Log message	Author	Age	Path
67	Changed BIST signals for RAMs.	tadejm	7900d 21h	/pci/tags/rel_6/rtl/
66	Changed empty status generation in pciw_fifo_control.v	mihad	7904d 07h	/pci/tags/rel_6/rtl/
65	Cleaned up non-blocking assignments in combinatinal logic statements	mihad	7907d 06h	/pci/tags/rel_6/rtl/
63	Added additional testcase and changed rst name in BIST to trst	mihad	7907d 10h	/pci/tags/rel_6/rtl/
62	Added BIST signals for RAMs.	mihad	7910d 03h	/pci/tags/rel_6/rtl/
60	Added support for Virtual Silicon two port RAM. Didn't run regression on it yet!	mihad	7918d 03h	/pci/tags/rel_6/rtl/
59	Added meta flop module for easier meta stable FF identification during synthesis	mihad	7918d 04h	/pci/tags/rel_6/rtl/
58	Removed all logic from asynchronous reset network	mihad	7923d 04h	/pci/tags/rel_6/rtl/
57	Added completion expiration test for WB Slave unit. Changed expiration signalling	mihad	7923d 10h	/pci/tags/rel_6/rtl/
56	Number of state bits define was removed	mihad	7924d 01h	/pci/tags/rel_6/rtl/