URL https://opencores.org/ocsvn/pci/pci/trunk

Subversion Repositories pci

[/] [pci/] [tags/] [rel_7/] - Rev 87

Rev	Log message	Author	Age	Path
63	Added additional testcase and changed rst name in BIST to trst	mihad	7927d 18h	/pci/tags/rel_7/
62	Added BIST signals for RAMs.	mihad	7930d 11h	/pci/tags/rel_7/
60	Added support for Virtual Silicon two port RAM. Didn't run regression on it yet!	mihad	7938d 11h	/pci/tags/rel_7/
59	Added meta flop module for easier meta stable FF identification during synthesis	mihad	7938d 12h	/pci/tags/rel_7/
58	Removed all logic from asynchronous reset network	mihad	7943d 12h	/pci/tags/rel_7/
57	Added completion expiration test for WB Slave unit. Changed expiration signalling	mihad	7943d 18h	/pci/tags/rel_7/
56	Number of state bits define was removed	mihad	7944d 09h	/pci/tags/rel_7/
55	Changed state machine encoding to true one-hot	mihad	7944d 09h	/pci/tags/rel_7/
54	Changed Tsetup and Thold for WISHBONE models, due to difficulties encountered during gate level sim	mihad	7977d 11h	/pci/tags/rel_7/
53	Updated for synthesis purposes. Gate level simulation was failing in some configurations	mihad	7977d 14h	/pci/tags/rel_7/