URL https://opencores.org/ocsvn/pci/pci/trunk

Subversion Repositories pci

[/] [pci/] [tags/] [rel_7/] [rtl/] [verilog/] - Rev 110

Rev	Log message	Author	Age	Path
63	Added additional testcase and changed rst name in BIST to trst	mihad	7939d 16h	/pci/tags/rel_7/rtl/verilog/
62	Added BIST signals for RAMs.	mihad	7942d 09h	/pci/tags/rel_7/rtl/verilog/
60	Added support for Virtual Silicon two port RAM. Didn't run regression on it yet!	mihad	7950d 09h	/pci/tags/rel_7/rtl/verilog/
59	Added meta flop module for easier meta stable FF identification during synthesis	mihad	7950d 10h	/pci/tags/rel_7/rtl/verilog/
58	Removed all logic from asynchronous reset network	mihad	7955d 11h	/pci/tags/rel_7/rtl/verilog/
57	Added completion expiration test for WB Slave unit. Changed expiration signalling	mihad	7955d 16h	/pci/tags/rel_7/rtl/verilog/
56	Number of state bits define was removed	mihad	7956d 07h	/pci/tags/rel_7/rtl/verilog/
55	Changed state machine encoding to true one-hot	mihad	7956d 08h	/pci/tags/rel_7/rtl/verilog/
53	Updated for synthesis purposes. Gate level simulation was failing in some configurations	mihad	7989d 13h	/pci/tags/rel_7/rtl/verilog/
51	Fixed a bug and provided testcase for it. Target was responding to configuration cycle type 1 transactions.	mihad	7989d 17h	/pci/tags/rel_7/rtl/verilog/