URL https://opencores.org/ocsvn/pci/pci/trunk

Subversion Repositories pci

[/] [pci/] [tags/] [rel_7/] [rtl/] [verilog/] - Rev 114

Rev	Log message	Author	Age	Path
67	Changed BIST signals for RAMs.	tadejm	7959d 10h	/pci/tags/rel_7/rtl/verilog/
66	Changed empty status generation in pciw_fifo_control.v	mihad	7962d 20h	/pci/tags/rel_7/rtl/verilog/
65	Cleaned up non-blocking assignments in combinatinal logic statements	mihad	7965d 18h	/pci/tags/rel_7/rtl/verilog/
63	Added additional testcase and changed rst name in BIST to trst	mihad	7965d 22h	/pci/tags/rel_7/rtl/verilog/
62	Added BIST signals for RAMs.	mihad	7968d 15h	/pci/tags/rel_7/rtl/verilog/
60	Added support for Virtual Silicon two port RAM. Didn't run regression on it yet!	mihad	7976d 15h	/pci/tags/rel_7/rtl/verilog/
59	Added meta flop module for easier meta stable FF identification during synthesis	mihad	7976d 16h	/pci/tags/rel_7/rtl/verilog/
58	Removed all logic from asynchronous reset network	mihad	7981d 17h	/pci/tags/rel_7/rtl/verilog/
57	Added completion expiration test for WB Slave unit. Changed expiration signalling	mihad	7981d 23h	/pci/tags/rel_7/rtl/verilog/
56	Number of state bits define was removed	mihad	7982d 13h	/pci/tags/rel_7/rtl/verilog/