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[/] [pci/] [tags/] [rel_7/] [rtl/] [verilog/] - Rev 71

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Rev Log message Author Age Path
46 Include statement was enclosed in synosys translate off/on directive - repaired mihad 7997d 13h /pci/tags/rel_7/rtl/verilog/
45 Added a few testcases. Repaired wrong reset value for PCI_AM5 register. Repaired Parity Error Detected bit setting. Changed PCI_AM0 to always enabled(regardles of PCI_AM0 define), if image 0 is used as configuration image mihad 7998d 18h /pci/tags/rel_7/rtl/verilog/
35 Files updated with missing includes, resolved some race conditions in test bench mihad 8143d 22h /pci/tags/rel_7/rtl/verilog/
33 Added some testcases, removed un-needed fifo signals mihad 8159d 18h /pci/tags/rel_7/rtl/verilog/
32 Added include statement that was missing and causing errors mihad 8167d 14h /pci/tags/rel_7/rtl/verilog/
26 Modified testbench and fixed some bugs mihad 8173d 13h /pci/tags/rel_7/rtl/verilog/
23 *** empty log message *** mihad 8191d 13h /pci/tags/rel_7/rtl/verilog/
21 Repaired a few bugs, updated specification, added test bench files and design document mihad 8191d 14h /pci/tags/rel_7/rtl/verilog/
19 *** empty log message *** mihad 8191d 14h /pci/tags/rel_7/rtl/verilog/
18 *** empty log message *** mihad 8191d 15h /pci/tags/rel_7/rtl/verilog/

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