URL https://opencores.org/ocsvn/pci/pci/trunk

Subversion Repositories pci

[/] [pci/] [tags/] [rel_8/] [rtl/] [verilog/] - Rev 117

Rev	Log message	Author	Age	Path
69	Changed BIST signal names etc..	mihad	7934d 04h	/pci/tags/rel_8/rtl/verilog/
68	Changed wrong signal name scanb_sen into scanb_en.	tadejm	7937d 13h	/pci/tags/rel_8/rtl/verilog/
67	Changed BIST signals for RAMs.	tadejm	7937d 18h	/pci/tags/rel_8/rtl/verilog/
66	Changed empty status generation in pciw_fifo_control.v	mihad	7941d 04h	/pci/tags/rel_8/rtl/verilog/
65	Cleaned up non-blocking assignments in combinatinal logic statements	mihad	7944d 03h	/pci/tags/rel_8/rtl/verilog/
63	Added additional testcase and changed rst name in BIST to trst	mihad	7944d 07h	/pci/tags/rel_8/rtl/verilog/
62	Added BIST signals for RAMs.	mihad	7947d 00h	/pci/tags/rel_8/rtl/verilog/
60	Added support for Virtual Silicon two port RAM. Didn't run regression on it yet!	mihad	7954d 23h	/pci/tags/rel_8/rtl/verilog/
59	Added meta flop module for easier meta stable FF identification during synthesis	mihad	7955d 01h	/pci/tags/rel_8/rtl/verilog/
58	Removed all logic from asynchronous reset network	mihad	7960d 01h	/pci/tags/rel_8/rtl/verilog/