URL https://opencores.org/ocsvn/pci/pci/trunk

Subversion Repositories pci

[/] [pci/] [tags/] [rel_WB_B3/] - Rev 78

Rev	Log message	Author	Age	Path
55	Changed state machine encoding to true one-hot	mihad	7986d 20h	/pci/tags/rel_WB_B3/
54	Changed Tsetup and Thold for WISHBONE models, due to difficulties encountered during gate level sim	mihad	8019d 21h	/pci/tags/rel_WB_B3/
53	Updated for synthesis purposes. Gate level simulation was failing in some configurations	mihad	8020d 01h	/pci/tags/rel_WB_B3/
52	Oops, never before noticed that OC header is missing	mihad	8020d 05h	/pci/tags/rel_WB_B3/
51	Fixed a bug and provided testcase for it. Target was responding to configuration cycle type 1 transactions.	mihad	8020d 05h	/pci/tags/rel_WB_B3/
50	Got rid of undef directives	mihad	8022d 21h	/pci/tags/rel_WB_B3/
49	Extracted distributed RAM module from wb/pci_tpram.v to its own file, got rid of undef directives	mihad	8022d 21h	/pci/tags/rel_WB_B3/
48	Extracted distributed RAM module from wb/pci_tpram.v to its own file	mihad	8022d 21h	/pci/tags/rel_WB_B3/
47	Known issues repaired	mihad	8023d 03h	/pci/tags/rel_WB_B3/
46	Include statement was enclosed in synosys translate off/on directive - repaired	mihad	8027d 21h	/pci/tags/rel_WB_B3/