URL https://opencores.org/ocsvn/pci/pci/trunk

Subversion Repositories pci

[/] [pci/] [tags/] [rel_WB_B3/] - Rev 91

Rev	Log message	Author	Age	Path
67	Changed BIST signals for RAMs.	tadejm	7923d 03h	/pci/tags/rel_WB_B3/
66	Changed empty status generation in pciw_fifo_control.v	mihad	7926d 13h	/pci/tags/rel_WB_B3/
65	Cleaned up non-blocking assignments in combinatinal logic statements	mihad	7929d 11h	/pci/tags/rel_WB_B3/
64	The testcase I just added in previous revision repaired	mihad	7929d 14h	/pci/tags/rel_WB_B3/
63	Added additional testcase and changed rst name in BIST to trst	mihad	7929d 15h	/pci/tags/rel_WB_B3/
62	Added BIST signals for RAMs.	mihad	7932d 08h	/pci/tags/rel_WB_B3/
60	Added support for Virtual Silicon two port RAM. Didn't run regression on it yet!	mihad	7940d 08h	/pci/tags/rel_WB_B3/
59	Added meta flop module for easier meta stable FF identification during synthesis	mihad	7940d 10h	/pci/tags/rel_WB_B3/
58	Removed all logic from asynchronous reset network	mihad	7945d 10h	/pci/tags/rel_WB_B3/
57	Added completion expiration test for WB Slave unit. Changed expiration signalling	mihad	7945d 16h	/pci/tags/rel_WB_B3/