URL https://opencores.org/ocsvn/pci/pci/trunk

Subversion Repositories pci

[/] [pci/] [tags/] [rel_WB_B3/] - Rev 94

Rev	Log message	Author	Age	Path
71	Changed the code a bit to make it more readable. Functionality not changed in any way. More robust synchronization in fifos is still pending.	mihad	7892d 05h	/pci/tags/rel_WB_B3/
69	Changed BIST signal names etc..	mihad	7929d 13h	/pci/tags/rel_WB_B3/
68	Changed wrong signal name scanb_sen into scanb_en.	tadejm	7932d 22h	/pci/tags/rel_WB_B3/
67	Changed BIST signals for RAMs.	tadejm	7933d 03h	/pci/tags/rel_WB_B3/
66	Changed empty status generation in pciw_fifo_control.v	mihad	7936d 14h	/pci/tags/rel_WB_B3/
65	Cleaned up non-blocking assignments in combinatinal logic statements	mihad	7939d 12h	/pci/tags/rel_WB_B3/
64	The testcase I just added in previous revision repaired	mihad	7939d 14h	/pci/tags/rel_WB_B3/
63	Added additional testcase and changed rst name in BIST to trst	mihad	7939d 16h	/pci/tags/rel_WB_B3/
62	Added BIST signals for RAMs.	mihad	7942d 09h	/pci/tags/rel_WB_B3/
60	Added support for Virtual Silicon two port RAM. Didn't run regression on it yet!	mihad	7950d 09h	/pci/tags/rel_WB_B3/