URL https://opencores.org/ocsvn/pci/pci/trunk

Subversion Repositories pci

[/] [pci/] [tags/] [rel_WB_B3/] [rtl/] - Rev 121

Rev	Log message	Author	Age	Path
71	Changed the code a bit to make it more readable. Functionality not changed in any way. More robust synchronization in fifos is still pending.	mihad	7883d 13h	/pci/tags/rel_WB_B3/rtl/
69	Changed BIST signal names etc..	mihad	7920d 21h	/pci/tags/rel_WB_B3/rtl/
68	Changed wrong signal name scanb_sen into scanb_en.	tadejm	7924d 06h	/pci/tags/rel_WB_B3/rtl/
67	Changed BIST signals for RAMs.	tadejm	7924d 11h	/pci/tags/rel_WB_B3/rtl/
66	Changed empty status generation in pciw_fifo_control.v	mihad	7927d 21h	/pci/tags/rel_WB_B3/rtl/
65	Cleaned up non-blocking assignments in combinatinal logic statements	mihad	7930d 19h	/pci/tags/rel_WB_B3/rtl/
63	Added additional testcase and changed rst name in BIST to trst	mihad	7930d 23h	/pci/tags/rel_WB_B3/rtl/
62	Added BIST signals for RAMs.	mihad	7933d 16h	/pci/tags/rel_WB_B3/rtl/
60	Added support for Virtual Silicon two port RAM. Didn't run regression on it yet!	mihad	7941d 16h	/pci/tags/rel_WB_B3/rtl/
59	Added meta flop module for easier meta stable FF identification during synthesis	mihad	7941d 18h	/pci/tags/rel_WB_B3/rtl/