URL https://opencores.org/ocsvn/pci/pci/trunk

Subversion Repositories pci

[/] [pci/] [trunk/] [bench/] [verilog/] - Rev 154

Rev	Log message	Author	Age	Path
81	Updated synchronization in top level fifo modules.	mihad	7798d 12h	/pci/trunk/bench/verilog/
73	Bug fixes, testcases added.	mihad	7807d 18h	/pci/trunk/bench/verilog/
69	Changed BIST signal names etc..	mihad	7899d 21h	/pci/trunk/bench/verilog/
66	Changed empty status generation in pciw_fifo_control.v	mihad	7906d 22h	/pci/trunk/bench/verilog/
64	The testcase I just added in previous revision repaired	mihad	7909d 22h	/pci/trunk/bench/verilog/
63	Added additional testcase and changed rst name in BIST to trst	mihad	7910d 00h	/pci/trunk/bench/verilog/
62	Added BIST signals for RAMs.	mihad	7912d 17h	/pci/trunk/bench/verilog/
57	Added completion expiration test for WB Slave unit. Changed expiration signalling	mihad	7926d 00h	/pci/trunk/bench/verilog/
54	Changed Tsetup and Thold for WISHBONE models, due to difficulties encountered during gate level sim	mihad	7959d 17h	/pci/trunk/bench/verilog/
52	Oops, never before noticed that OC header is missing	mihad	7960d 01h	/pci/trunk/bench/verilog/