URL https://opencores.org/ocsvn/pci/pci/trunk

Subversion Repositories pci

[/] [pci/] [trunk/] [rtl/] - Rev 154

Rev	Log message	Author	Age	Path
115	Added signals for WB Master B3.	tadejm	7599d 10h	/pci/trunk/rtl/
113	ifdefs moved to thier own lines, this confuses some of the tools.	simons	7606d 13h	/pci/trunk/rtl/
111	synchronizer_flop replaced with pci_synchronizer_flop, artisan ram instance updated.	simons	7606d 18h	/pci/trunk/rtl/
110	Module that converts slave WISHBONE B3 accesses to WISHBONE B2 accesses with CAB.	mihad	7608d 17h	/pci/trunk/rtl/
108	Added 'three_left_out' to pci_pciw_fifo signaling three locations before full. Added comparison between current registered cbe and next unregistered cbe to signal wb_master whether it is allowed to performe burst or not. Due to this, I needed 'three_left_out' so that writing to pci_pciw_fifo can be registered, otherwise timing problems would occure.	tadejm	7612d 14h	/pci/trunk/rtl/
106	Added limited WISHBONE B3 support for WISHBONE Slave Unit. Doesn't support full speed bursts yet.	mihad	7617d 13h	/pci/trunk/rtl/
104	Found and simulated the problem in the synchronization logic. Repaired the synchronization logic in the FIFOs.	mihad	7622d 22h	/pci/trunk/rtl/
94	Changed one critical PCI bus signal logic.	mihad	7669d 21h	/pci/trunk/rtl/
88	Added the reset value parameter to the synchronizer flop module. Added resets to all synchronizer flop instances. Repaired initial sync value in fifos.	mihad	7747d 18h	/pci/trunk/rtl/
86	Entered the option to disable no response counter in wb master.	mihad	7759d 15h	/pci/trunk/rtl/