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199 Check out in the design document for changes made on Load logic, a load chain has been added to Memblock I/O and several memory blocks were removed, under construction, this version WONT in any means work jguarin2002 4478d 23h /raytrac/
198 Check out for the best out for the best organization so the datapath does not consume to many logic cells jguarin2002 4478d 23h /raytrac/
197 Chnages on interconnectivity: Check out the SGDMA Sheets jguarin2002 4489d 00h /raytrac/
196 raytrac+sg_dma+raytrac. Step One, the DPC is transformed. Now there are five instructions (check the design document), theres no full queue sync event, there are only four result queues and only 3 add fp 32 b adders rather than 4. Even it seems like a reduction has taken place, decodification efforts take place when decoding multiplexation from arithmetic blocks towards the resulting queues jguarin2002 4492d 11h /raytrac/
195 Document advance and changes in the design jguarin2002 4495d 08h /raytrac/
194 Work In Progress jguarin2002 4510d 13h /raytrac/
193 WIP: Main Document jguarin2002 4511d 11h /raytrac/
192 Some change I dont realize what is it in the design document (xls) jguarin2002 4511d 22h /raytrac/
191 Reduced the implementation of Instruction Queue to 16 instructions rather than 32 and using registers in logic cells rather than M9Ks memory blocks.... finally the design fits. jguarin2002 4511d 22h /raytrac/
190 M9K Block reduction. And Altera Compiler Directive was added to adder code to prevent unnecesary M9K block inferring... jguarin2002 4516d 07h /raytrac/

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