URL https://opencores.org/ocsvn/rise/rise/trunk

Subversion Repositories rise

[/] [rise/] [trunk/] [vhdl/] - Rev 102

Rev	Log message	Author	Age	Path
78	Added stall_in to sensitivity list.	jlechner	6393d 08h	/rise/trunk/vhdl/
77	- Fixed case.	cwalter	6393d 08h	/rise/trunk/vhdl/
76	- Changed order of some statements to improve readability.	cwalter	6393d 08h	/rise/trunk/vhdl/
75	- Added barrel shifter implementation.	cwalter	6393d 08h	/rise/trunk/vhdl/
74	- Fixed bug where register value used by load was passed through to write back. Correct is ALU value.	cwalter	6393d 10h	/rise/trunk/vhdl/
73	- Fixed bug where immediate value for LD_IMM_HB was placed in the upper 8bits. This is done by the execute stage.	cwalter	6393d 10h	/rise/trunk/vhdl/
72	Added RISE_PACK_SPECIFIC containing either - constants declarations for synthesis or - enumeration types for simulation Added call to conversion function where a std_logic_vector is assigned to a opcode signal or a condition signal.	jlechner	6393d 19h	/rise/trunk/vhdl/
71	Added RISE_PACK_SPECIFIC containing either - constants declarations for synthesis or - enumeration types for simulation	jlechner	6393d 19h	/rise/trunk/vhdl/
70	Moved opcode and conditional constants and opcode_t and cond_t data types to rise_const_pack.vhd.	jlechner	6393d 19h	/rise/trunk/vhdl/
69	Synthesis package containing opcode and conditional constants used in other vhd files. Package also contains convert functions from std_logic_vector to the appropriate data type.	jlechner	6393d 19h	/rise/trunk/vhdl/