URL https://opencores.org/ocsvn/rise/rise/trunk

Subversion Repositories rise

[/] [rise/] [trunk/] [vhdl/] - Rev 126

Rev	Log message	Author	Age	Path
104	- Added missing signal dmem_data_in.	cwalter	6412d 15h	/rise/trunk/vhdl/
102	changed data pitch	ustadler	6414d 20h	/rise/trunk/vhdl/
101	- Signals for memory block where not always set. This resulted in a latch.	cwalter	6414d 21h	/rise/trunk/vhdl/
100	- Signal clear_in was missing in sensitivity list.	cwalter	6414d 21h	/rise/trunk/vhdl/
99	- Fixed problem with barrel shifter input signals where a latch has been synthesized.	cwalter	6414d 21h	/rise/trunk/vhdl/
98	- Applied indenting tool.	cwalter	6414d 21h	/rise/trunk/vhdl/
97	Fixed bug: only set branch and clear signals if branch is actually executed.	jlechner	6414d 22h	/rise/trunk/vhdl/
96	- SR register is now computed in ALU stage.	cwalter	6414d 22h	/rise/trunk/vhdl/
95	- Write back now only updates SR in case of a LOAD.	cwalter	6414d 22h	/rise/trunk/vhdl/
94	Added signal from ex stage to register lock unit for clearing all register locks when a branch is executed.	jlechner	6414d 22h	/rise/trunk/vhdl/