URL https://opencores.org/ocsvn/rise/rise/trunk

Subversion Repositories rise

[/] [rise/] [trunk/] [vhdl/] - Rev 135

Rev	Log message	Author	Age	Path
112	Uart drin aber signale nicht eingebunden	trinklhar	6408d 22h	/rise/trunk/vhdl/
111	- Fixed bug where certain opcodes did not check for availability of registers.	cwalter	6411d 13h	/rise/trunk/vhdl/
110	- Added missing file to CVS.	cwalter	6411d 20h	/rise/trunk/vhdl/
107	- Added new example for memory testing.	cwalter	6412d 12h	/rise/trunk/vhdl/
106	- ALUOP1_LD_MEM_BIT must be checked within ALUOP1_WB_REG_BIT.	cwalter	6412d 12h	/rise/trunk/vhdl/
105	- OPCODE_ST_DISP must not set ALUOP1_WB_REG_BIT.	cwalter	6412d 12h	/rise/trunk/vhdl/
104	- Added missing signal dmem_data_in.	cwalter	6412d 13h	/rise/trunk/vhdl/
102	changed data pitch	ustadler	6414d 18h	/rise/trunk/vhdl/
101	- Signals for memory block where not always set. This resulted in a latch.	cwalter	6414d 18h	/rise/trunk/vhdl/
100	- Signal clear_in was missing in sensitivity list.	cwalter	6414d 18h	/rise/trunk/vhdl/