URL https://opencores.org/ocsvn/s1_core/s1_core/trunk

Subversion Repositories s1_core

[/] [s1_core/] [trunk/] [hdl/] - Rev 105

Rev	Log message	Author	Age	Path
54	Updated filelists	fafa1971	6126d 01h	/s1_core/trunk/hdl/
53	Removed from CVS tree because header file preprocessing is done elsewhere	fafa1971	6126d 01h	/s1_core/trunk/hdl/
52	Updated SPARC Core files from OpenSPARC T1 version 1.4 to version 1.5	fafa1971	6126d 01h	/s1_core/trunk/hdl/
51	User Chris "gaterocket" corrected a couple of errors for FPGA boards: blocking assignments and two uninitialized variables.	fafa1971	6212d 01h	/s1_core/trunk/hdl/
48	Updated with new OpenSPARC 1.4 list	fafa1971	6276d 23h	/s1_core/trunk/hdl/
46	Fresh version from OpenSPARC 1.4 and Icarus define preprocessing	fafa1971	6276d 23h	/s1_core/trunk/hdl/
45	I'm going to remove original OpenSPARC 1.4 files so that I can insert again the ones with Icarus Verilog preprocessor already applied by update_sparccore (it seems that Xilinx's XST does NOT support defines at compile time)	fafa1971	6277d 00h	/s1_core/trunk/hdl/
44	Embedded `defines into Verilog source since did not find command line option for XST	fafa1971	6277d 22h	/s1_core/trunk/hdl/
39	Empty modules for cacheless Simply RISC S1 Core	fafa1971	6277d 22h	/s1_core/trunk/hdl/
25	Updated filelists according to the new OpenSPARC 1.4, and add some minor changes like Stephen Williams's suggestion to use $(S1_ROOT) in the filelists for Icarus Verilog (he's the author!).	fafa1971	6292d 00h	/s1_core/trunk/hdl/