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[/] [s1_core/] [trunk/] [hdl/] - Rev 112

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Rev Log message Author Age Path
55 Nobody remembers why these blackboxed files were required! fafa1971 6126d 07h /s1_core/trunk/hdl/
54 Updated filelists fafa1971 6126d 07h /s1_core/trunk/hdl/
53 Removed from CVS tree because header file preprocessing is done elsewhere fafa1971 6126d 07h /s1_core/trunk/hdl/
52 Updated SPARC Core files from OpenSPARC T1 version 1.4 to version 1.5 fafa1971 6126d 07h /s1_core/trunk/hdl/
51 User Chris "gaterocket" corrected a couple of errors for FPGA boards: blocking assignments and two uninitialized variables. fafa1971 6212d 07h /s1_core/trunk/hdl/
48 Updated with new OpenSPARC 1.4 list fafa1971 6277d 05h /s1_core/trunk/hdl/
46 Fresh version from OpenSPARC 1.4 and Icarus define preprocessing fafa1971 6277d 06h /s1_core/trunk/hdl/
45 I'm going to remove original OpenSPARC 1.4 files so that I can insert again
the ones with Icarus Verilog preprocessor already applied by update_sparccore
(it seems that Xilinx's XST does NOT support defines at compile time)
fafa1971 6277d 06h /s1_core/trunk/hdl/
44 Embedded `defines into Verilog source since did not find command line option for XST fafa1971 6278d 04h /s1_core/trunk/hdl/
39 Empty modules for cacheless Simply RISC S1 Core fafa1971 6278d 04h /s1_core/trunk/hdl/

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