URL https://opencores.org/ocsvn/s1_core/s1_core/trunk

Subversion Repositories s1_core

[/] [s1_core/] [trunk/] [tools/] - Rev 76

Rev	Log message	Author	Age	Path
39	Empty modules for cacheless Simply RISC S1 Core	fafa1971	6328d 18h	/s1_core/trunk/tools/
38	Changed to compile (for now) the boot code.	fafa1971	6332d 17h	/s1_core/trunk/tools/
31	Removed list of formerly dirty signals, to improve waveforms readability.	fafa1971	6342d 19h	/s1_core/trunk/tools/
27	Added "tee" to see output both on screen and saved in the logfile.	fafa1971	6342d 20h	/s1_core/trunk/tools/
26	Added "tee" commands to see the output both on screen and saved on logfile.	fafa1971	6342d 20h	/s1_core/trunk/tools/
16	Added the 3 new defines to make the design: - synthesizable for FPGA - single-threaded - without the cryptographic SPU unit	fafa1971	6343d 07h	/s1_core/trunk/tools/
15	Removed the remove of CVS subdirs...	fafa1971	6343d 08h	/s1_core/trunk/tools/
13	Added first version of small tool to reverse engineer the boot code used by the T1.	fafa1971	6403d 01h	/s1_core/trunk/tools/
12	Updated the PCX/CPX fields description with all the info required for debugging.	fafa1971	6403d 17h	/s1_core/trunk/tools/
11	Corrected the bug about the packet format, now we are near to perfection...	fafa1971	6403d 20h	/s1_core/trunk/tools/