URL https://opencores.org/ocsvn/sdhc-sc-core/sdhc-sc-core/trunk

Subversion Repositories sdhc-sc-core

[/] [sdhc-sc-core/] - Rev 167

Rev	Log message	Author	Age	Path
147	Sd-Core: + Added checking of Busy signal after write	rkastl	4923d 16h	/sdhc-sc-core/
146	SdClockMaster: + fixed output of data at negedge of sclk in high speed mode	rkastl	4923d 16h	/sdhc-sc-core/
145	Verification: + SdCardModel and SdBFM seperated	rkastl	4923d 16h	/sdhc-sc-core/
144	Simulation files for tbTbdSd created. tbTbdSd is not done and TestWbMaster seems to be lost.	rkastl	4923d 16h	/sdhc-sc-core/
143	Ignore pattern: + work + modelsim.ini + vsim.wlf + transcript + cycloneii and altera_mf generated library folders	rkastl	4923d 16h	/sdhc-sc-core/
142	Thesis: PDF added to .gitignore	rkastl	4923d 16h	/sdhc-sc-core/
141	Added *.bak to ignore file.	rkastl	4923d 16h	/sdhc-sc-core/
140	Removed tbSdData-Bhv-ea.vhdl. Non-automated tb, tested in complete verification tb anyway.	rkastl	4923d 16h	/sdhc-sc-core/
139	Removed Testbench for unitSdWbSlave. Again: weak tb and it´s tested in the complete verification environment anyway.	rkastl	4923d 16h	/sdhc-sc-core/
138	Removed testbench for unitSdCmd because it was a weak testbench and the functionality is tested in the SdVerificationTestbench anyway.	rkastl	4923d 16h	/sdhc-sc-core/