URL https://opencores.org/ocsvn/sdhc-sc-core/sdhc-sc-core/trunk

Subversion Repositories sdhc-sc-core

[/] [sdhc-sc-core/] [trunk/] - Rev 160

Rev	Log message	Author	Age	Path
140	Removed tbSdData-Bhv-ea.vhdl. Non-automated tb, tested in complete verification tb anyway.	rkastl	4919d 14h	/sdhc-sc-core/trunk/
139	Removed Testbench for unitSdWbSlave. Again: weak tb and it´s tested in the complete verification environment anyway.	rkastl	4919d 14h	/sdhc-sc-core/trunk/
138	Removed testbench for unitSdCmd because it was a weak testbench and the functionality is tested in the SdVerificationTestbench anyway.	rkastl	4919d 14h	/sdhc-sc-core/trunk/
137	Regression test suite: Removed unneeded testbenches from the makefile. Only complete reusable blocks are tested from now on.	rkastl	4919d 14h	/sdhc-sc-core/trunk/
136	SDHC: - SdData refactored to use a single counter - TestWbMaster added to TbdSd (not functional yet)	rkastl	4919d 14h	/sdhc-sc-core/trunk/
135	Multiple-Inclusion-Protection to SystemVerilog files added Stops using relative paths in `includes. instead +incdir has to be used.	rkastl	4919d 14h	/sdhc-sc-core/trunk/
134	SdData: Further refactoring.	rkastl	4919d 14h	/sdhc-sc-core/trunk/
133	SdData: Further refactoring	rkastl	4919d 14h	/sdhc-sc-core/trunk/
132	SdData: Refactoring, not done. Testbench works again, but does not really test anything.	rkastl	4919d 14h	/sdhc-sc-core/trunk/
131	SdClockMaster added to regression tests	rkastl	4919d 14h	/sdhc-sc-core/trunk/