URL https://opencores.org/ocsvn/sdhc-sc-core/sdhc-sc-core/trunk

Subversion Repositories sdhc-sc-core

[/] [sdhc-sc-core/] [trunk/] - Rev 168

Rev	Log message	Author	Age	Path
148	SdVerification: + CardModel: Execution thread which starts initialization and then receives token and parses them. TbdSd: + Added SdWbSdSynchronization.	rkastl	4919d 21h	/sdhc-sc-core/trunk/
147	Sd-Core: + Added checking of Busy signal after write	rkastl	4919d 21h	/sdhc-sc-core/trunk/
146	SdClockMaster: + fixed output of data at negedge of sclk in high speed mode	rkastl	4919d 21h	/sdhc-sc-core/trunk/
145	Verification: + SdCardModel and SdBFM seperated	rkastl	4919d 21h	/sdhc-sc-core/trunk/
144	Simulation files for tbTbdSd created. tbTbdSd is not done and TestWbMaster seems to be lost.	rkastl	4919d 21h	/sdhc-sc-core/trunk/
143	Ignore pattern: + work + modelsim.ini + vsim.wlf + transcript + cycloneii and altera_mf generated library folders	rkastl	4919d 21h	/sdhc-sc-core/trunk/
142	Thesis: PDF added to .gitignore	rkastl	4919d 21h	/sdhc-sc-core/trunk/
141	Added *.bak to ignore file.	rkastl	4919d 21h	/sdhc-sc-core/trunk/
140	Removed tbSdData-Bhv-ea.vhdl. Non-automated tb, tested in complete verification tb anyway.	rkastl	4919d 21h	/sdhc-sc-core/trunk/
139	Removed Testbench for unitSdWbSlave. Again: weak tb and it´s tested in the complete verification environment anyway.	rkastl	4919d 21h	/sdhc-sc-core/trunk/